公司创业初期,已获得知名投资机构的战略投资,公司坐落于上海浦东新区张江高科技园区内,欢迎希望致力于该技术领域的各类人才加入公司。公司将为员工提供良好的福利待遇和各类培训。 主要福利可能包括:

- 五险一金

- 补充公积金

- 午餐、交通津贴

- 员工补充医疗保险、双子女医疗保险

- 股权激励计划

- 全面健康管理、健身活动

招聘信息

Job description:

1. Responsible for software development of AI hardware accelerators

2.Work with ASIC team to co-validate the design, driver and SW.

3.Integrate and optimize accelerator backend for popular machine learning frameworks

4.Develop and optimize computation library.

 

Minimum Requirements:

1.MS with 2+years or BS with 3+ years’ experience in SW/driver development.

2.Familiar with C++ and python

3.One of the following skills

4.Familiar with Linux driver

5. Familiar with LLVM/gcc compiler

6.Familiar with OpenCL/OpenGL driver

7. Familiar with CUDA

8.Familiar with Caffe/Tensorflow/PyTorch/etc. and CNN/RNN operators

9.Strong problem solving, teamwork and communication skills


Job description:

1.Participate in architecture level discussion by closely working with design architects.

2.IP level design spec and RTL coding

3.Coworking with synthesis and physical design team on the ASIC implementation plan.

4.Coworking with verification engineers on the function/performance test plan.

 

Minimum Requirements:

1.MS with 2+years or BS with 3+ years’ experience in ASIC/SoC design

2.Strong hands-on verilog development experience

3.Familiar with scripting languages like Perl, Makefile, …

4.Familiar with DSP, ARM, AXI is a plus

5.Knowledge on memory controller, PCIE is a big plus.

6.Strong problem solving, teamwork and communication skills.


Job description:

1.Work on AI machine learning project verification using SystemVerilog, UVM or C++.

2.Coworking with architects and design engineers on the function/performance test plan.

3.Responsible for test cases development and debug.

4.Implement directed and random testcase in UVM/SV/C++, as well as checkers and assertions.

5.Doing coverage analysis and bug cleanup in regression.

Minimum Requirements:

1.MS with 2+years or BS with 3+ years experience in ASIC/SoC design verification.

2.Experience in any PCIE/DDR/Video/ARM/DSP/MCU verification is a big plus.

3. Knowledge of complex SoC DV flow from plan to coverage.

4.Strong problem solving and communication skills, team player.

5.Familiar with scripting languages like Perl, Makefile is a plus.

Job description:

1.Participate in SOC full Chip DFT feature and architecture definition.

2.Implement SOC DFT function including SCAN, MBIST, BSD, Analog Macro test logic.Perform verification on all DFT structures.

3.Generate DFT related timing constraints and work with PD team for timing closure.

4.Generate and verify DFT structural patterns and functional patterns.

5.Participate in ATE bring-up and debug DFT patterns on ATE.

6.Design and implement other DFX (debug, characterization, yield etc).

Minimum Requirements:

1.BS/MS with 2+ years' related experience designing DFT for SOCs.

2.Solid knowledge of DFT including scan, boundary scan, BIST and JTAG.

3.Familiar with basic Mentor/ Synopsys DFT flow and tools.

4.Basic knowledge of IC design flow, including coding, simulation, verification, synthesis and STA.

5.Skill and efficiency in scripting using common UNIX scripting languages such as TCL, Perl, csh.

6.Strong experience with Verilog RTL design and simulation.

7.Good English communication skills.

8.Self-motivated and good team player.


Job description:

1.Work with Front-End design team and physical design team for large scale ASIC chip physical implementation.

2.Focus on physical design of deep sub-micron AI chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc.

Minimum Requirements:

1.MSEE with 0+ years or Bachelor with 2+ years of industrial experience in ASIC design.

2.Hands on experience in large scale ASIC chip physical design.

3.Knowledgeable in all aspects of deep submicron ASIC design flow.

4.Successfully gone through several complete product development cycles.

5.Demonstrate strong leadership and work well with cross-functional teams.

6.Good listening, writing and speaking English

7.Good communication skills, strong interpersonal skills and the flexibility

8.Dedicated, hard working and good team player

9.Familiar with Back-End (physical design) EDA tools

10.Familiar with Front-End EDA tools is a plus

11.Familiar with Unix/Linux environment and good at scripts


Job description:

Work with Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron AI chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. The individual is also expected to be accountable for project delivery.

Minimum Requirements:

1.MSEE with 5+ years or Bachelor with 7+ years of industrial experience in ASIC design.

2.5+ years or more years of experience in physical design of deep submicron digital ASIC chips.

3.Hands on experience in large scale ASIC chip physical design.

4.Knowledgeable in all aspects of deep submicron ASIC design flow.

5.Successfully gone through several complete product development cycles.

6.Demonstrate strong leadership and work well with cross-functional teams.

7.Good listening, writing and speaking English.

8.Good communication skills, strong interpersonal skills and the flexibility.

9.Dedicated, hard working and good team player.

10.Familiar with Back-End (physical design) EDA tools.

11.Familiar with Front-End EDA tools is a plus.

12.Familiar with Unix/Linux environment and good at scripts.


Job description:

Work with Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron AI chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc.

The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. The individual is also expected to be accountable for project delivery.

Minimum Requirements:

1.MSEE with 8+ years or Bachelor with 10+ years of industrial experience in ASIC design.

2.8+ years or more years of experience in physical design of deep submicron digital ASIC chips.

3.Hands on experience in large scale ASIC chip physical design.

4.Knowledgeable in all aspects of deep submicron ASIC design flow.

5.Successfully gone through several complete product development cycles.

6.Demonstrate strong leadership and work well with cross-functional teams.

7.Good listening, writing and speaking English.

8.Good communication skills, strong interpersonal skills and the flexibility.

9.Dedicated, hardworking and good team player.

10.Familiar with Back-End (physical design) EDA tools.

11.Familiar with Front-End EDA tools is a plus.

12.Familiar with Unix/Linux environment and good at scripts.


Job description:

1. PCB schematic/layout的设计、器件选型及功能实现;

2. 熟悉元器件库创建维护

3. 协助进行信号完整性和电源方面的仿真与分析

4. 负责和设计团队沟通PCB设计及封装设计规则.

5. 熟练操作常用调试仪器,制订测试方案,完成硬件调试和测试工作 


Minimal requirement

1. 本科,5年以上工作经验,电子相关专业优先

2. EMC/EMI相关经验

3. 良好团队协作与沟通能力

4. 熟悉PCIEDDR等高速接口者优先


Job description:

1. SoC architecture definition according to product spec.

2. Architecting and coding for SoC level RTL design, including clock/reset/interrupt units, IO logic, low-power control, etc.

3. Responsible for RTL lint/CDC, logic synthesis, static timing analysis, formal verification and power analysis.

4. Work with PnR engineers to solve issues related to the digital IP physical implementation and timing closure.

5. Work with software engineers, hardware engineers to complete the chip system debugging.


Minimum Requirements:

1. BS/MS degree with minimum 5+ years' experience in ASIC design related positions is a must.

2. Solid Verilog RTL coding skills plus good understanding of clock, reset, sync/async interface, timing, etc.

3. Experience in AMBA, clock/PLL control units, peripheral/interface/PCIE/DDR IP design is highly preferred.

4. Solid understanding of state-of-art SoC development flow and methodology from RTL to GDS.

5. Strong hands-on experience in using widely-adopted EDA tools for netlist generation, formal check and timing fix.

6. Experience with automation using scripting techniques such as PERL, Python and TCL.

7. Good spoken and written English.

8. Self-motivation, result oriented, good team work and communication skills.

Job description:

1. SoC level RTL design, including clock/reset/interrupt units, IO logic, low-power control, etc.

2. Responsible for RTL quality check and SOC integration.

3. Responsible for synthesis, static timing analysis and formal verification.

 

Minimum Requirements:

1. BS/MS degree with minimum 2+ years' experience in ASIC design related positions is a must.

2. Familiar with hardware description languages such as Verilog.

3. Familiar with IC design tool flow with hands-on experience in front-end EDA tools like Spyglass, DC, formality and PT.

4. Practical experience in Perl and TCL programming is a plus.

5. Good spoken and written English.

6. Self-motivation, result oriented, good team work and communication skills.

Job description

Co-work with IP architect to define IP C model spec.

Base on C model spec to implement bus accurate or cycle accurate C model.

Provide the golden reference base on C model user case to support IP RTL development and verification .

Provide software interface in C model to support software development.

Analysis performance base on C model enviroment and feedback to architect prons and cons.

 

Minimum Requirements:

M.S with 5+ years' hands-on experience on IP C model development.

Be farmiliar with Transaction level modeling or Cycle based modeling technique

Be master at System C IP modelling framework

Be expert on Python, Perl, Verilog or other scripts is a plus.

Have knowledge on Computer architecture and AI network/algorithm is a big plus.

Good debug skill and communication skill are required.

Job description:

1. IP level design spec and RTL coding.

2. Co-work with other designers to develop assertions for IP and SOC.

3. Formal property verification for IP and SOC.

4. Co-work with synthesis and physical design team on the ASIC implementation plan.

5. Co-work with Power architect to do IP power optimization.

6. Co-work with verification team on the function/performance test plan.

Minimum Requirements:

1. MS with 2+ years' or BS with 3+ years' experience in ASIC design.

2. Strong hands-on Verilog/System-verilog development experience.

3. Strong hands-on System verilog assertion development experience.

4. Familiar with scripting languages like Perl, Makefile, etc.

5. Familiar with DSP, ARM, AXI is a plus.

6. Familiar with formal property verification flow is a big plus.

7. Knowledge on power optimization flow (Power Artist, PtPx) is a big plus.

8. Knowledge on memory controller, PCIE is a big plus.

9. Strong problem solving, teamwork and communication skills.

Job description:

Co-work with IP architect to define IP C model spec.  

Base on C model spec to implement bus accurate or cycle accurate C model.

Provide the golden reference base on C model user case to support  IP RTL development and verification .

Provide software interface in C model to support software development.

Analysis performance base on C model enviroment and feedback to architect prons and cons.

Minimum Requirements:

M.S with 5+ years' hands-on experience on IP C model development.  

Be farmiliar with Transaction level modeling or Cycle based modeling  technique

Be master at System C IP modelling framework

Be expert on Python, Perl, Verilog or other scripts is a plus.

Have knowledge on Computer architecture and AI network/algorithm is a big plus.

Good debug skill and communication skill are required.

Job description:

负责以下一项或全部工作:

1、 Linux内核、Linux驱动开发和调试;

2、 基于芯片bare metal环境下的功能验证开发及调试;

3、 Bootloader、芯片IP驱动开发;

4、 Linux APPSDKBSP软件开发;

5、 为客户研发提供底层软件支持。

Minimum Requirements:

1、 计算机、电子、通信等专业本科及以上学历;

2、 3年以上的基于X86ARM 平台的Linux驱动开发经验;

3、 具备bare metal驱动开发经验;

4、 具有很强的C/C++编程能力,具备一定的汇编语言编程能力;

5、 有半导体公司核心BSP开发团队工作经验者尤佳;

6、 DDRPCIEethernetSDvideo codec 其中一种或多种驱动开发经验者尤佳;

7、 具有AI 芯片软件开发经验、各种AI网络常用算子实现的工作经验尤佳;

Job description:

1、 DSP 固件开发;

2、 DSP 视觉算法软件开发;

3、 DSP 软件指令、算法优化;

4、 为客户研发提供底层软件支持。

Minimum Requirements:

1、 计算机、电子、通信等专业本科及以上学历;

2、 3年以上DSP软件开发经验,至少对一种DSP 硬件架构、运行机制理解深刻;

3、 具有很强的C/C++编程能力,具备DSP汇编语言编程能力;

4、 具有AI 芯片软件开发经验、各种AI网络常用算子实现的工作经验尤佳;

5、 有半导体公司核心BSP开发团队工作经验者尤佳

Job description:

负责以下一项或全部工作:

1、 MCU 固件开发;

2、 基于芯片bare metal环境下的功能验证开发及调试;

3、 芯片IP驱动开发;

4、 为客户研发提供底层软件支持。

Minimum Requirements:

1、 计算机、电子、通信等专业本科及以上学历;

2、 MCU 硬件架构理解深刻、具备bare metal驱动开发经验;

3、 具有很强的C/C++编程能力,具备一定的汇编语言编程能力;

4、 具有AI 芯片软件开发经验、各种AI网络常用算子实现的工作经验尤佳;

5、 有半导体公司核心BSP开发团队工作经验者尤佳;

6、 DDRPCIEethernetSDvideo codecpower 其中一种或多种驱动开发经验者尤佳;

Job description:

负责以下一项或全部工作:

1.流媒体服务器软件架构设计与开发;

2.实时音、视频传输服务器软件开发;

Minimum Requirements:

1. 计算机、电子、通信等专业本科及以上学历,5年以上开发经验;

2. 有大型音视频平台相关开发经验,了解行业标准GB/T28181ONVIF等;

3. 精通Linux环境TCP/UDP网络开发,熟悉RTP/RTCP/RTSP/RTMP/SIP等流媒体协议;

4. 熟悉H264/H265/AAC/MPEG等音视频编解码格式和算法

5. 熟悉ffmpeg/live555/kurento等开源项目,有基于开源项目开发经验的优先

6. 具有很强的C/C++编程能力,具备一定的汇编语言编程能力;

7. 具有AI 芯片软件开发经验、各种AI网络常用算子实现的工作经验尤佳;

Job description:

负责以下一项或全部工作:

1. Linux应用软件接口架构设计与开发;

2. 实时音、视频传输服务器软件开发;

3. 芯片SDK设计和开发;

4. FPGA & SOC 验证、测试和demo 应用程序开发;

5. Linux 软件系统、驱动的性能分析与优化;

Minimum Requirements:

1. 计算机、电子、通信等专业本科及以上学历,3年以上开发经验;

2. 熟悉嵌入式开发,有ARM Cortex-A 平台开发经验;

3. 熟悉Linux环境TCP/UDP网络开发,熟悉RTP/RTCP/RTSP/RTMP/SIP等流媒体协议;

4. 熟悉H264/H265/AAC/MPEG等音视频编解码格式和算法

5. 熟悉ffmpeg/live555/kurento等开源项目,有基于开源项目开发经验的优先

6. 具有很强的C/C++编程能力,具备一定的汇编语言编程能力;

7. 具有AI 芯片软件开发经验、各种AI网络常用算子实现的工作经验尤佳;

8. 有半导体公司核心BSP开发团队工作经验者尤佳

Job description:

作为资深软件结构工程师,参与公司的整体软件架构设计并且和多个软件,硬件和架构部门紧密合作

2 参与和领导软件层面的产品的定义,开发,量产和客户支持

 

Minimum Requirements:

1、计算机、电子、通信等专业硕士及以上学历;

2、有半导体公司核心软件架构团队工作经验者尤佳;

312年以上的基于X86ARM 平台的软件架构和开发经验;

4、熟悉嵌入式开发,有ARM Cortex-A 平台开发经验;

5、具有AI 芯片软件开发经验;

6、熟悉H264/H265/MPEG等音视频编解码格式和算法;

7DSP软件开发经验,至少对一种DSP 硬件架构、运行机制理解深刻;

8、具有很强的C/C++编程能力,具备一定的汇编语言编程能力;

9有很强的软件架构大局观已经上面多项具体软件方面的多年业界经验

10、有很强的沟通和协作能力,和良好的团队合作精神

11、有很强的分析和解决问题能力

Job description:

1. IP/SOC设计团队合作进行自研AI芯片的SW/FW/HW协同设计及验证

2. 对自研AI芯片编程模型进行抽象以便于软件开发

 

Minimum Requirements:

1. 熟悉C/C++

2. 熟悉CUDA/OpenCL者尤佳

3. 熟悉计算机系统体系结构者尤佳

4. 熟悉主流深度学习网络模型者尤佳

5. 熟悉XLA/TVM/Glow/OpenVINO/TensorRTAI编译器者尤佳

1. 熟悉LLVM/GCC等编译器者尤佳

Job description:

1. IP/SOC团队合作进行SW/FW/HW协同设计及验证

2. 规划固件架构以最大限度发挥CPU/MCU/DSP性能

 

Minimum Requirements:

1. 熟悉C语言;

2. 熟悉主流CPU/MCU/DSP编程模型;

3. 具有AI加速芯片相关开发软件经验者尤佳;

4. 具有H264/H265/MPEG等音视频编解码格式和算法者尤佳。

Job description:

1.芯片密码算法驱动开发和验证;

2.指导芯片开发人员进行硬件模块设计实现和验证;

3.研究、跟进芯片安全相关的攻击和防护技术;

4.指导设计人员在安全硬件模块中加入对应的防护措施;

5.撰写开发文档,以及商密产品型号申请所需的技术文档;

 

Minimum Requirements:

1. 信息安全、密码学、数学、计算机相关专业硕士及以上学历 1年以上工作经验; 

2. 熟悉国内外安全算法; 

3. 熟悉 C/C++ 语言;  

4. 熟悉硬件攻击理论和实践; 

5. 热衷于技术工作,具有较强的学习、沟通和团队合作能力。

Job description:

-H264/HEVC等视频编码器的驱动及中间层软件;

-编写与所开发代码配套的流程图,设计文档等;

 

Minimum Requirements:

-熟悉C/C++编程

-熟悉Linux环境下驱动开发

-对视频编解码的原理和码流格式有一定了解;

-有视频相关的驱动/中间件/应用层代码编写/调试经验;

Job description:

1.  Work on AI machine learning project verification using SystemVerilog, UVM or C++.

2. Lead verification team members for SOC verification.

3. Lead the verification efforts in the projects and mentor/guide the team members.

4. Setup verification plan and SOC DV environment.

5. Close coverage measures to identify verification holes and to show progress towards tape-out.

6. Project execution tracking and signoff.

 

Minimum Requirements:

1. MS with 8+years or BS with 10+ years experience in IP/SoC design verification, direct people management experience.

2. Good communication skills in both Chinese and English.

3. Complex SOC design verification background, direct experience in IP/SOC DV.

4.  Solid background with ASIC design verification flow and multiple ASIC tape out experience.

5. Solid knowledge on SystemVerilog, C/C++, Verilog.

6. Solid knowledge on scripting language like perl, python.

7. Solid knowledge on UVM/OVM.

8. Experience in PCIE/DDR/Video DV.

Job description:

1.Work on SOC project emulation.

2. Develop emulation system infrastructure for both function and performance.

3. Bring up all interfaces and SOC end to end tests in emulation.

4. Support DV team and software team for function/peformance verification and driver/AI compiler development in emulator.

 

Minimum Requirements:

1.MS with 2+years or BS with 3+ years experience in ASIC/SoC emulation or design verification.

2. Good knowledge on C++/SV/Verilog/Perl/Python.

3. Zebu/Palladium/Veloce experience.

4. Familiar with PCIE/DDR/Video/AXI.

5. Understanding of Kernel and driver level software.

6. Good communication skills in both Chinese and English.